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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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32K x 8 Bit Static Random Access Memory
The MCM6706AR is a 262,144 bit static random access memory organized as 32,768 words of 8 bits, fabricated using high performance silicon-gate BiCMOS technology. Static design eliminates the need for external clocks or timing strobes. Output enable (G) is a special control feature that provides increased system flexibility and eliminates bus contention problems. The MCM6706AR meets JEDEC standards and is available in a revolutionary pinout 300 mil, 32-lead surface-mount SOJ package. Single 5.0 V 10% Power Supply Fully Static -- No Clock or Timing Strobes Necessary All Inputs and Outputs Are TTL Compatible Three State Outputs Fast Access Times: MCM6706AR-6 = 6 ns MCM6706AR-7 = 7 ns MCM6706AR-8 = 8 ns * Center Power and I/O Pins for Reduced Noise BLOCK DIAGRAM
A A A A A A A A A DQ0 INPUT DATA CONTROL DQ7 A COLUMN I/O COLUMN DECODER ROW DECODER MEMORY MATRIX 512 ROWS x 64 x 8 COLUMNS VCC VSS
MCM6706AR
J PACKAGE 300 MIL SOJ CASE 857-02
PIN ASSIGNMENT
A0 A1 A2 A3 E DQ0 DQ1 VCC VSS DQ2 DQ3 W A4 A5 A6 A7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 NC A14 A13 A12 G DQ7 DQ6 VSS VCC DQ5 DQ4 A11 A10 A9 A8 NC
* * * * *
PIN NAMES
A0 - A14 . . . . . . . . . . . . . . . . . . . . . . . Address W . . . . . . . . . . . . . . . . . . . . . . . . . Write Enable E . . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable G . . . . . . . . . . . . . . . . . . . . . . . Output Enable DQ0 - DQ7 . . . . . . . . . . . . Data Input/Output VCC . . . . . . . . . . . . . . . . + 5 V Power Supply VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . Ground NC . . . . . . . . . . . . . . . . . . . . . . No Connection
A
A
A
A
A
E W G
5/95
(c) Motorola, Inc. 1995 MOTOROLA FAST SRAM
MCM6706AR 1
TRUTH TABLE
E H L L L G X H L X W X H H L Mode Not Selected Read Read Write I/O Pin High-Z High-Z Dout Din Cycle -- -- Read Cycle Write Cycle
ABSOLUTE MAXIMUM RATINGS (See Note)
Rating Power Supply Voltage Voltage Relative to VSS for Any Pin Except VCC Output Current Power Dissipation Temperature Under Bias Operating Temperature Symbol VCC Vin, Vout Iout PD Tbias TA Value - 0.5 to + 7.0 - 0.5 to VCC + 0.5 30 2.0 - 10 to + 85 0 to + 70 Unit V V mA W C C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. This BiCMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained.
Storage Temperature -- Plastic Tstg - 55 to + 125 C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V 10%, TA = 0 to 70C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage (Operating Voltage Range) Input High Voltage Input Low Voltage Symbol VCC VIH VIL Min 4.5 2.2 - 0.5** Typ 5.0 -- -- Max 5.5 VCC + 0.3* 0.8 Unit V V V
* VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width 2.0 ns) or I 30.0 mA. ** VIL (min) = - 0.5 V dc @ 30.0 mA; VIL (min) = - 2.0 V ac (pulse width 2.0 ns) or I 30.0 mA.
DC CHARACTERISTICS
Parameter Input Leakage Current (All Inputs, Vin = 0 to VCC) Output Leakage Current (E = VIH or G = VIH, Vout = 0 to VCC) Output High Voltage (IOH = - 4.0 mA) Output Low Voltage (IOL = + 8.0 mA) Symbol Ilkg(I) Ilkg(O) VOH VOL Min -- -- 2.4 -- Max 1.0 1.0 -- 0.4 Unit A A V V
POWER SUPPLY CURRENTS
Parameter AC Active Supply Current (Iout = 0 mA, VCC = max, f = fmax) AC Standby Current (E = VIH, VCC = max, f = fmax) CMOS Standby Current (VCC = max, f = 0 MHz, E VCC - 0.2 V, Vin VSS, or VCC - 0.2 V) Symbol ICCA ISB1 ISB2 -6 235 95 20 -7 225 85 20 -8 215 75 20 Unit mA mA mA Notes 1, 2, 3 1, 2, 3
NOTES: 1. Reference AC Operating Conditions and Characteristics for input and timing (VIH/VIL, tr/tf, pulse level 0 to 3.0 V, VIH = 3.0 V). 2. All addresses transition simultaneously low (LSB) and then high (MSB). 3. Data states are all zero.
MCM6706AR 2
MOTOROLA FAST SRAM
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25C, Periodically Sampled Rather Than 100% Tested)
Parameter Address Input Capacitance Control Pin Input Capacitance (E, G, W) I/O Capacitance Symbol Cin Cin Cout Max 5 6 6 Unit pF pF pF
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V 10%, TA = 0 to + 70C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ns Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1A
READ CYCLE (See Notes 1 and 2)
-6 Parameter Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Output Hold from Address Change Chip Enable Low to Output Active Chip Enable High to Output High-Z Output Enable Low to Output Active Output Enable High to Output High-Z Symbol tAVAV tAVQV tELQV tGLQV tAXQX tELQX tEHQZ tGLQX tGHQZ Min 6 -- -- -- 2.5 3 0 0 0 Max -- 6 6 4 -- -- 3 -- 3 Min 7 -- -- -- 2.5 3 0 0 0 -7 Max -- 7 7 4 -- -- 3.5 -- 3.5 Min 8 -- -- -- 2.5 3 0 0 0 -8 Max -- 8 8 4 -- -- 3.5 -- 3.5 Unit ns ns ns ns ns ns ns ns ns 4 ,5, 6 4, 5, 6 4, 5, 6 4, 5, 6 Notes 3
NOTES: 1. W is high for read cycle. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles. 3. All read cycle timing is referenced from the last valid address to the first transitioning address. 4. At any given voltage and temperature, tEHQZ max < tELQX min, and tGHQZ max < tGLQX min, both for a given device and from device to device. 5. Transition is measured 200 mV from steady-state voltage with load of Figure 1B. 6. This parameter is sampled and not 100% tested. 7. Device is continuously selected (E = VIL, G = VIL). 8. Addresses valid prior to or coincident with E going low.
AC TEST LOADS
+5 V OUTPUT Z0 = 50 RL = 50 VL = 1.5 V OUTPUT 255 5 pF 480
TIMING LIMITS
The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time (even though most devices do not require it). On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time.
Figure 1A
Figure 1B
MOTOROLA FAST SRAM
MCM6706AR 3
READ CYCLE 1 (See Note 7)
tAVAV A (ADDRESS) tAXQX Q (DATA OUT) PREVIOUS DATA VALID tAVQV DATA VALID
READ CYCLE 2 (See Note 8)
tAVAV A (ADDRESS) tELQV E (CHIP ENABLE) tELQX G (OUTPUT ENABLE) tGLQX Q (DATA OUT) tAVQV tGLQV DATA VALID tGHQZ tEHQZ
MCM6706AR 4
MOTOROLA FAST SRAM
WRITE CYCLE 1 (W Controlled, See Notes 1 and 2)
MCM6706AR-6 Parameter Write Cycle Time Address Setup Time Address Valid to End of Write Write Pulse Width Data Valid to End of Write Data Hold Time Write Low to Data High-Z Write High to Output Active Write Recovery Time Symbol tAVAV tAVWL tAVWH tWLWH, tWLEH tDVWH tWHDX tWLQZ tWHQX tWHAX Min 6 0 6 6 3 0 0 3 0 Max -- -- -- -- -- -- 3.5 -- -- MCM6706AR-7 Min 7 0 7 7 3.5 0 0 3 0 Max -- -- -- -- -- -- 3.5 -- -- MCM6706AR-8 Min 8 0 8 8 3.5 0 0 3 0 Max -- -- -- -- -- -- 3.5 -- -- Unit ns ns ns ns ns ns ns ns ns 4, 5, 6 4, 5, 6 Notes 3
NOTES: 1. A write occurs during the overlap of E low and W low. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles. 3. All write cycle timings are referenced from the last valid address to the first transitioning address. 4. Transition is measured 200 mV from steady-state voltage with load of Figure 1B. 5. Parameter is sampled and not 100% tested. 6. At any given voltage and temperature, tWLQZ max is < tWHQX min both for a given device and from device to device.
WRITE CYCLE 1
tAVAV A (ADDRESS) tAVWH E (CHIP ENABLE) tWLEH tWLWH W (WRITE ENABLE) tAVWL tWHAX
tDVWH DATA VALID
tWHDX
D (DATA IN) tWLQZ Q (DATA OUT) HIGH-Z HIGH-Z
tWHQX
MOTOROLA FAST SRAM
MCM6706AR 5
WRITE CYCLE 2 (E Controlled, See Notes 1 and 2)
MCM6706AR-6 Parameter Write Cycle Time Address Setup Time Address Valid to End of Write Chip Enable to End of Write Data Valid to End of Write Data Hold Time Write Recovery Time Symbol tAVAV tAVEL tAVEH tELWH, tELEH tDVEH tEHDX tEHAX Min 6 0 6 5 3 0 0 Max -- -- -- -- -- -- -- MCM6706AR-7 Min 7 0 7 6 3.5 0 0 Max -- -- -- -- -- -- -- MCM6706AR-8 Min 8 0 8 6 3.5 0 0 Max -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns 4,5 Notes 3
NOTES: 1. A write occurs during the overlap of E low and W low. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles. 3. All write cycle timing is referenced from the last valid address to the first transitioning address. 4. If E goes low coincident with or after W goes low, the output will remain in a high impedance condition. 5. If E goes high coincident with or before W goes high, the output will remain in a high impedance condition.
WRITE CYCLE 2
tAVAV A (ADDRESS) tAVEH E (CHIP ENABLE) tAVEL W (WRITE ENABLE) tDVEH D (DATA IN) DATA VALID tEHDX tELWH tEHAX
tELEH
Q (DATA OUT)
HIGH-Z
ORDERING INFORMATION
(Order by Full Part Number) MCM 6706AR X
Motorola Memory Prefix Part Number
X
XX
Shipping Method (R2 = Tape and Reel, Blank = Rails) Speed (6 = 6 ns, 7 = 7 ns, 8 = 8 ns) Package (J = 300 mil SOJ)
Full Part Numbers -- MCM6706ARJ6 MCM6706ARJ6R2
MCM6706ARJ7 MCM6706ARJ7R2
MCM6706ARJ8 MCM6706ARJ8R2
MCM6706AR 6
MOTOROLA FAST SRAM
PACKAGE DIMENSIONS
32-LEAD 300 MIL SOJ CASE 857-02
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DATUM PLANE -X- LOCATED AT TOP OF MOLD PARTING LINE AND COINCIDENT WITH TOP OF LEAD, WHERE LEAD EXITS BODY. 4. TO BE DETERMINED AT PLANE -X-. 5. TO BE DETERMINED AT PLANE -T-. 6. DIMENSION A & B DO NOT INCLUDE MOLD PROTRUSION. MOLD PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 7. 857-01 IS OBSOLETE, NEW STANDARD 857-02. DIM A B C D E F G K L N P R S MILLIMETERS MIN MAX 20.83 21.08 7.50 7.74 3.26 3.75 0.41 0.50 2.24 2.48 0.67 0.81 1.27 BSC 0.89 1.14 0.64 BSC 0.76 1.14 8.38 8.64 6.60 6.86 0.77 1.01 INCHES MIN MAX 0.820 0.830 0.295 0.305 0.128 0.148 0.016 0.020 0.088 0.098 0.026 0.032 0.050 BSC 0.035 0.045 0.025 BSC 0.030 0.045 0.330 0.340 0.260 0.270 0.030 0.040
F 32 PL 0.17(0.007)
32 1 17
S
A
S
M
NOTE 4
16
-AL G -XDETAIL Z NOTE 3
D 32 PL 0.17(0.007) P 0.17(0.007) S B -B-
S S
A
NOTE 5 S
EC R 0.25 (0.010)
S
0.10 (0.004) -TSEATING PLANE
K
S RADIUS B
S NOTE 5
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
MOTOROLA FAST SRAM
MCM6706AR 7
Literature Distribution Centers: USA/EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan. ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong.
MCM6706AR 8
CODELINE TO BE PLACED HERE
*MCM6706AR/D*
MCM6706AR/D MOTOROLA FAST SRAM

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